1. Field of the Invention
The invention relates to computer systems having PCI bus architecture and, more particularly, to supporting a subtractive agent on the secondary side of a PCI-to-PCI bridge in such systems.
2. Description of the Related Art
The peripheral component interconnect, or PCI, bus has been well received by computer system board designers since its introduction in 1992. The PCI bus is referred to as a mezzanine bus, or a local bus, because it usually has resided between the very high performance processor bus and the lower performance ISA or EISA bus.
As personal computer users demand ever increasing processing power, the PCI bus has allowed computational workload to be transferred from the central processing unit, or CPU, itself, to peripheral devices on the PCI bus. Increasingly, the computational workload has been transferred to masters. Masters, or initiators, initiate bus transactions while bus slaves, or targets, respond to a bus transaction initiated by a bus master. Oftentimes, an initiator is on one bus and a target is on a second bus. An agent is any entity or device that operates on a computer bus. An agent can be either a bus master or bus slave.
The PCI bus is by design limited to ten loads. A PCI device incorporated onto the motherboard is essentially one load and a PCI slot is considered two loads. For the needs of many computers, ten loads may be too limiting. So, many system boards contain multiple PCI buses. The logic that connects one computer bus to another is known as a bridge. The PCI-to-PCI bridge thus has a PCI bus on both sides of it. The PCI bus closer to the microprocessor, or CPU, is known as the primary PCI bus, or primary bus; the other PCI bus is known as the secondary PCI bus. When a transaction goes across the PCI-to-PCI bridge, the bus on which the master resides is a master bus and the bus on which the target resides is a target bus.
The PCI-to-PCI bridge therefore has two interfaces, a primary and a secondary interface. A master device or a target device can reside on either interface. Thus, for transactions where the master bus is different from the target bus, the PCI-to-PCI bridge functions as an intermediary, or go-between amid the master and target devices. First, it retrieves the transaction from the master on behalf of the target; second, it sends the transaction to the target on behalf of the master. From the perspective of the master, the PCI-to-PCI bridge is a target on the master bus on behalf of the target that resides on the target bus. Likewise, from the perspective of the target device, the PCI-to-PCI bridge is a master on the target bus on behalf of the master device that resides on the master bus.
The bridge provides a low latency path through which the processor may directly access PCI devices mapped anywhere in the memory or I/O address space of the computer system. The bridge maps the address space of one bus into the address space of another bus. The PCI bus defines three physical address spaces: memory, I/O space, and configuration space. Address decoding on the PCI bus is distributed; i.e. each device coupled to the PCI bus performs address decoding.
The PCI specification defines two styles of address decoding: positive and subtractive. Positive decoding is faster since each PCI device is looking for accesses in the address range(s) to which the device has been assigned. Subtractive decoding can be implemented by only one device on the PCI bus, since the subtractive decoding device accepts all accesses not positively decoded by some other agent.
Another aspect of positive decoding is inverse decoding (or mapping), which looks for accesses in the address ranges(s) that are not in the address assignments. For example, the PCI-to-PCI bridge is given an address map of the devices residing on the secondary PCI bus. When a cycle is initiated on the primary PCI bus, the PCI-to-PCI bridge performs a positive decode based on the address map. However, if the cycle is initiated on the secondary PCI bus, the PCI-to-PCI bridge performs a positive decode based on the inverse of the address map (that is, if the address is not on the map, then the bridge positively decodes the cycle).
More details on the PCI bus are found in Chapter 3 of the PCI Local Bus Specification, Production Version, Revision 2.1, dated Jun. 1, 1995, and the PCI-to-PCI Bridge Architecture Specification, Rev. 1.0, Apr. 5, 1994. Both documents are published by the PCI Special Interest Group of Hillsboro, Oreg. and are hereby incorporated by reference.
One way to configure a PCI bridge is to program its address map with the devices located on its secondary bus. Using this addressing scheme, a bridge positively decodes transactions occurring on the primary bus to determine if the destination of the transaction is to the secondary bus (across the bridge). The address map tells the bridge the address ranges in which the bridge is to forward transactions downstream from the primary to the secondary bus.
On a PCI bus, there are three speeds at which a device can positively decode addresses and claim a transaction as its own. "Fast" devices claim a transaction one clock after the address is placed on the bus; "medium" devices claim a transaction two clock cycles after; and "slow" devices claim the transaction after three clocks. Subtractive decoding can occur only when no device positively claims the transaction. Further, as noted, only one subtractive agent can be on a PCI bus.
The presence of subtractive agents on a PCI bus complicates the ability of the bridge to keep track of all agents on its secondary side. This is because of the way the address map of a bridge is created. When a computer is powered on, an operating system is loaded at the end of the boot process. The operating system creates the address map for each bridge in the system by determining the address allocation for each plug-and-play device that resides on the secondary side of the bridge. Subtractive agents typically are not allocated any address region until the device drivers coupled to them are loaded. Device drivers are not loaded until after the operating system is loaded. Thus, the address map of each bridge does not reflect the presence of a subtractive device.
A bridge itself may act as a subtractive agent, provided no other subtractive agents reside on its primary bus. As the bridge is the subtractive agent for the primary bus, a second subtractive agent can reside on the secondary bus. The bridge effectively assists the subtractive agent in claiming transactions intended for it from masters on the primary bus.
A problem arises, however, with subtractive agents on the secondary bus when a master, also on the secondary bus, initiates a transaction. Because of the addressing scheme described above, a bridge can erroneously claim a transaction initiated on the secondary bus (based on the inverse decode of the bridge address map) and forward it to the primary bus. The subtractive target on the secondary bus thus does not receive the intended transaction. This results in a master abort (since the transaction will not be claimed by any of the devices on the primary bus) and a system error.
One solution to this problem has been to only place subtractive devices on the primary PCI bus. Such a solution, however, is not feasible in a portable computer environment where the primary PCI bus is on the system board of the notebook computer itself and the secondary PCI bus is part of the docking station's hardware. Because the docking station supports an ISA bus, a subtractive agent between the PCI and ISA buses of the docking station needs to be maintained.